Location:Home > T SERIES > Turbo Undefined 5 > Patente US20140332805

Patente US20140332805

Time:2018-02-12 08:25Turbochargers information Click:

Patente US20140332805

The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device including an inverter circuit. The present invention also relates to an electronic device including the semiconductor device.

BACKGROUND ART

[0002]

In recent years, a semiconductor device with low power consumption has started to be used as a component in an electronic device for a reduction in the power consumption of the electronic device. An electronic device includes a variety of circuits such as a CPU, an interface circuit, and a memory element. These circuits are connected by an input circuit, an output circuit, or an input/output circuit.

[0003]

As an input circuit, an output circuit, and an input/output circuit, a buffer circuit or a three-state inverter (also referred to as “tri-state inverter”) circuit is used. In the three-state inverter circuit, output is set to the following three states: “High (HI),” “Low (LO),” and “High impedance (HIZ).”

[0004]

“High” of the three-state inverter circuit means that the potential of an output terminal is set to the highest potential of the power supply voltage terminal; “Low” thereof means that the potential of the output terminal is set to the lowest potential; and “High impedance” thereof means that the output terminal is set in a floating state.

[0005]

Transistors included in a three-state inverter each have leakage current, so that leakage of charges or inflow of charges occurs even when the transistor is not selected. Thus, even when the three-state inverter is brought into a high impedance state, leakage current flows to an output terminal through the transistor included in the three-state inverter, which results in an insufficient reduction in power consumption. Further, voltage drop occurs, which causes malfunction.

[0006]

Patent Document 1 discloses a flip-flop circuit using a three-state inverter in which a transistor with high threshold voltage and a transistor with low threshold voltage are provided together to reduce leakage current flowing when the flip-flip circuit does not operate.

[0007]

However, in Patent Document 1, high power supply voltage is needed in consideration of the transistor with high threshold voltage in order to secure the operation of the transistor with high threshold voltage. Further, the transistors are each thought to be a transistor formed using a silicon material, and leakage current is kept flowing in the transistors even when the transistors are turned off. Thus, a sufficient reduction in power consumption is not achieved.

REFERENCE

[0000]

[Patent Document 1] Japanese Published Patent Application No. 2001-223563

DISCLOSURE OF INVENTION

[0009]

In view of the above problem, an object of one embodiment of the disclosed invention is to provide a semiconductor device in which leakage current in high impedance can be suppressed to reduce power consumption.

[0010]

Another object of one embodiment of the disclosed invention is to provide a semiconductor device in which an increase in size of a circuit can be suppressed and leakage current can be suppressed.

[0011]

Another object of one embodiment of the disclosed invention is to provide a semiconductor device in which a circuit can be downsized and leakage current can be suppressed.

[0012]

In the disclosed invention, a semiconductor device is formed using a purified oxide semiconductor. A transistor formed using a purified oxide semiconductor has extremely small leakage current; thus, power consumption can be reduced. Further, malfunctions of the semiconductor device at the time of high impedance due to leakage current can be prevented.

[0013]

One embodiment of the disclosed invention is a semiconductor device which includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. A gate of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. One of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor. The other of the source and the drain of the third transistor is electrically connected to a high-potential wiring. A gate of the third transistor is electrically connected to a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor. The other of the source and the drain of the fourth transistor is electrically connected to a low-potential wiring. Channel formation regions of the third transistor and the fourth transistor are each formed using an oxide semiconductor material.

[0014]

In the above structure, the third transistor and the fourth transistor can be provided over the first transistor and the second transistor.

[0015]

Copyright infringement? Click Here!

Related reading
Related recommend